1. Field of the Invention
The invention relates to a multilayer wiring device for packaging integrated circuit chips, and more particularly to an electrical interconnect device with power and ground lines interwoven about signal line layers and capacitive vias between signal layers so as to make efficient use of the signal layer surface area and interlayer space and provide decoupling capacitance while reducing or eliminating the need for separate power and ground layers and external capacitors.
2. Description of Related Art
In the manufacture of integrated circuits, silicon wafers containing many individual integrated circuits are fabricated and then the wafers are cut into individual integrated circuit chips or die. The chips are subsequently packaged and interconnected to other electrical components. During packaging, electrically conductive metal leads can be bonded between a chip and an interconnect substrate to provide proper electrical interconnection between different chips.
Current multi-chip circuitry design requires the attachment of numerous integrated circuit chips to high density electrical interconnects, also known as multi-chip modules (MCMs) or as substrates. The electrical interconnects normally include surface pads for bonding to surface mounted chips, a dielectric, and electrical lines buried in the dielectric for connecting selected pads to provide electrical routing between various bond sites on the chips. It is common to use copper for the buried lines and polyimide as the dielectric. The copper lines may form separate layers of orthogonal wiring sets that are interconnected to one another and to surface pads by vertical conductive vias such as metal pillars.
As integrated circuit technology advances towards even larger scale integration and high performance circuits, the number of drivers which can switch simultaneously on a chip also increases. This imposes stringent requirements on the power supply system which has to supply high current transients during short time intervals without causing any noise signals in the power distribution system. Noise signals can propagate in the power distribution system and cause false switching if they reach quiescent drivers.
Accordingly, there are typically two functions accomplished in a multilayer interconnect structure. One is the electrical performance such as power distribution (e.g. by power and ground lines), impedance matching and minimal cross talk. The other is the actual interconnect or signal routing. Conventional multilayer structures generally separate these functions into distinct layers. Some layers are assigned to power distribution, other layers to signal routing. An example of prior art multilayer wiring substrates with a plurality of power supply layers formed within the substrates is disclosed in U.S. Pat. No. 4,816,323 to Inoue entitled "Multilayer Wiring Substrate." Power distribution layers often serve as reference planes for the signals in order to create a transmission line environment with controlled impedances. But having separate layers reduces the effectiveness of power distribution in stripline environments. In addition, power distribution layers are often produced with very course granularity as relatively simple structures in metal planes with little or no fine feature patterning. This results in a cost penalty for producing a relatively simple structure with a complicated process.
Attempts have been made to solve this problem by producing power and ground layers in a technology different than that used to produce the routing or signal layers. An example is thin film wiring layers on a co-fired ceramic base. Co-fired ceramic can produce coarse geometies with relatively low cost, particularly by fabricating simple layers with simple processes and complex layers with complex processes. Copper-polyimide on co-fired ceramic is an example.
Another key aspect of electrical interconnect devices is impedance control. There are three basic ways to achieve a controlled impedance environment for a conductor. The first is a microstrip, which is generally a single ground or reference plane above or below the conductor. The second is a strip line, in which the conductor is sandwiched between two reference planes, for instance one above and one below. And the third is co-planar wave guide, in which reference planes are closely positioned on either side of the conductor.
Furthermore, as electrical interconnect devices achieve fine geometries, narrow signal lines with wide spaces therebetween become necessary to prevent cross-talk between adjacent signal lines. As a result, the fraction of area on a typical routing layer that contains metal becomes quite small. That is, routing layers fabricated by precise design rules suffer low surface area utilization with much non-metallized topology in order to electrically accommodate the fine signal lines. But for greater produceability there should be as few metallization layers as possible.
Various approaches to providing power distribution systems in multilayer wiring substrates are as follows:
U.S. Pat. No. 4,072,816 by Gedney et al. entitled "Integrated Circuit Package" discloses a prepunched copper-dielectric laminate ground plane assembly placed on a ceramic substrate around surface mounted components. The ground plane is connected to selected circuit connection pins by welding or soldering.
U.S. Pat. No. 4,322,778 to Barbour et al. entitled "High Performance Semiconductor Packaging Assembly" discloses a power supply distribution system consisting of a radial waveguide structure with parallel waveguide planes located between signal fan-out wiring and internal wiring metallurgy.
U.S. Pat. No. 4,628,411 by Balderes et al. entitled "Apparatus For Directly Powering A Multi-Chip Module From A Power Distribution Bus" discloses a module powered directly from a power distribution bus via voltage tabs mounted on the edge of the module rather than from the bus via power distribution planes within the board.
U.S. Pat. No. 4,866,507 to Jacobs et al. entitled "Module for Packaging Semiconductor Integrated Circuit Chips On A Base" discloses thin film wiring layers having coplanar signal, power and ground lines with at least one power or ground line existing between coplanar signal lines to minimize cross talk. To facilitate power distribution, lines of specific power levels of the patterned planes are connected to lines of the same power level on other patterned planes. While Jacobs et al. represents a significant advance over the art of record, there still remains portions of unused space, in particular between power and ground lines in separate planes. Furthermore, decoupling capacitors are described as being incorporated either on the top surface of the module or in the base substrate itself by appropriately doping the base substrate. That is, Jacobs fails to describe how capacitors can be located within the existing wiring structure.
As a result, there exists a need for an electrical interconnect device that achieves a reduction of power distribution layers and/or an increased signal layer area utilization while also providing adequate impedance control and decoupling capacitance.